1)½ÇÀü¸ðÀÇ°í»ç
- Âü&°ÅÁþ ¹®Á¦¿¡¼´Â º¸±â¿¡¼ ¸ð¼ø °ü°èÀΰͺÎÅÍ È®ÀÎÇÏ¿© °æ¿ìÀÇ ¼ö¸¦ ¸¸µé±â
- ½Ã°£ ¹èºÐ¿¡ ¾ÆÁ÷ ¾î·Á¿òÀ» ´À³¦ -> Àΰ¿¡¼ ¹è¿î SKILLÀ» ¿¬½ÀÇÏ¿© Àû±ØÀûÀ¸·Î ½Ã°£ ¹èºÐ¿¡ ÀǽÄÇϱâ
2) Memory ¹ÝµµÃ¼
- Flash memory
Floating gate -> Charge trap layer·Î ¹ßÀü
Tunneling Oxide : ÀüÀÚµéÀÌ Tunneling ÇÒ¼ö ÀÖ´Â Oxide(¸Å¿ì ¾ã´Ù.)
Floating gate, Charge trap layer -> ÀüÀÚµéÀ» ÀúÀåÇϴ â°í °°Àº ¿ªÇÒ but material°ú Ư¡ÀÌ ´Ù¸§
Nand flash memoryÀÇ ±¸µ¿ ¿ø¸®
write, read, erase¸¦ ¼³¸íÇÒ¼ö ÀÖ¾î¾ß ÇÑ´Ù.
write ±¸µ¿
control gate¿¡ +·Î °ÇÏ°Ô ¹ÙÀ̾¸¦ °É¸é floating ¹× charge trap Ãþ¿¡ ÀüÀÚµéÀÌ Åͳθµ ÇÏ¸é¼ °¤È÷°Ô µÇ°í ÀÌÈÄ
¹ÙÀ̾°¡ »ç¶óÁö¸é channelÀÌ »ç¶óÁ®µµ floating ¹× charge trap Ãþ¿¡´Â ÀüÀÚµéÀÌ ³²¾ÆÀÖ°Ô µÈ´Ù.
erase ±¸µ¿
control gate¿¡ -·Î °ÇÏ°Ô ¹ÙÀ̾¸¦ °É¸é floating ¹× charge trap Ãþ¿¡ ÀüÀÚµéÀÌ ¹Ý´ë·Î ÅͳθµµÇ¸é¼ ³ª°¡°ÔµÈ´Ù.
read ±¸Á¾
°¢ MOSFET ¼ÒÀÚÀÇ threshold voltage(Vth)¸¦ È®ÀÎ
NAND flash memoryÀÇ ¹ßÀü
1. floating gate -> Charge trap layer
2. SLC->MLC->TLC->QLC
ÀåÁ¡ : ÁýÀûµµ Áõ°¡
´ÜÁ¡ : ½Å·Ú¼º °¨¼Ò(DATA ½ÅÈ£ Æø °¨¼Ò), ¼ö¸í °¨¼Ò(ÇÊ¿ä Àü¾Ð Áõ°¡¿¡ µû¸¥ Àý¿¬ Æı«(Wear leveling technique·Î ´ë
ÀÀ)
3. 3D NAND
¼öÁ÷À¸·Î ½×´Â ¹æ½Ä
ÀåÁ¡ : ÁýÀûµµ Áõ°¡ -> °¡°Ý °æÀï·Â Çâ»ó
´ÜÁ¡ : °øÁ¤ º¹Àâµµ Áõ°¡ -> ¼öÀ²ÀÌ ³·¾ÆÁú¼ö ÀÖ´Ù.(¾çÇ°·ü Ç϶ô°¡´É¼º)
- RAM
DRAMÀÇ ±¸µ¿¹æ½Ä
sense amplifier : DRAM¿¡¼ ÀúÀåµÈ ¸Þ¸ð¸®¸¦ °è¼ÓÇؼ refreshÇØ ÁÖ´Â ¿ªÇÒ (±¸µ¿¿ø¸® ÀÌÇØÇϱâ)
Â÷¼¼´ë RAM : PRAM, STT-MRAM, RRAM
PRAM(»óº¯È), STT-MRAM(ÀÚ±âÀ庯È-ÀüÀÚ½ºÇÉÀÌ¿ë), RRAM(ÀúÇ×-Ceramic °°Àº ºÎµµÃ¼ÀÇ defect ÀÌ¿ë)